1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to semiconductor chip package substrates and methods of making the same.
2. Description of the Related Art
Many current integrated circuits are formed as multiple dice on a common silicon wafer. After the basic process steps to form the circuits on the dice are complete, the individual dice are cut from the wafer. The cut dice are then usually mounted to structures, such as circuit boards, or packaged in some form of enclosure.
One frequently-used package consists of a substrate upon which a die is mounted. The upper surface of the substrate includes electrical interconnects. The die is manufactured with a plurality of bond pads. A collection of solder bumps are provided between the bond pads of the die and substrate interconnects to establish ohmic contact. An underfill material is deposited between the die and the substrate to act as a material that prevents damage to the solder bumps due to mismatches in the coefficients of thermal expansion between the die and the substrate, and an adhesive to hold the die. The substrate interconnects include an array of solder pads that are arranged to line up with the die solder bumps. After the die is seated on the substrate, a reflow process is performed to enable the solder bumps of the die to metallurgically bond to the solder pads of the substrate.
One conventional type of substrate consists of a core laminated between upper and lower build-up layers. The core itself usually consists of four layers of glass filled epoxy. The build-up layers, which may number four or more on opposite sides of the core, are formed from some type of resin. Various metallization structures are interspersed in the core and build-up layers in order to provide electrical pathways between pins, pads or other solder balls on the lowermost layer of the substrate and the pads that bond with the chip solder bumps. The pins, pads or solder balls are designed to electrically interface with a pin grid array socket, a land grid array socket or a ball grid array land pattern of another electrical device, such as a printed circuit board.
The core provides a certain stiffness to the substrate. Even with that provided stiffness, conventional substrates still tend to warp due to mismatches in coefficients of thermal expansion for the chip, underfill and substrate. However, there is a need to provide shorter electrical pathways in package substrates in order to lower power supply inductance and improve power fidelity for power transferred through the substrate. The difficult problem is how to reduce the electrical pathways without inducing potentially damaging substrate warping.
One conventional technique for shoring up the stiffness of a chip package substrate involves the mounting of a stiffener ring to an upper side of the package substrate. These types of conventional stiffeners are frequently fabricated from copper, aluminum or steel and require an adhesive to adhere to the substrate.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.